Memory ICs comprise a plurality of memory cells interconnected by bitlines and wordlines. A memory cell includes a transistor coupled to a capacitor for storage of a bit of information. A gate terminal of the transistor is coupled to a wordline, a first terminal of the transistor is coupled to a bitline, and a second terminal of the transistor is coupled to a plate of the capacitor. The other plate of the capacitor, for example, is coupled to a reference voltage, such as VDD/2 or ground. For ferroelectric memory cells, the other plate of the capacitor is coupled to a plateline.
To realize a high density memory ICs, the memory cells employ a capacitor over plug structure (COP), as shown in FIG. 1. The structure includes a capacitor 160 having a dielectric layer 165 located between first and second electrodes 161 and 162. The capacitor is coupled to a conductive plug 170. The plug, for example, is coupled to a diffusion region of a transistor. Depending on the application, a barrier layer 188 can be used to prevent diffusion of oxygen to the plug. Such barrier layers are particularly useful for ferroelectric or high k dielectric applications. When polysilicon (poly-Si) is used to form the plug, a metal suicide layer 181 is disposed between the plug and capacitor.
FIGS. 2-4 show a conventional process for forming the COP structure. As shown, an interlevel dielectric layer 230 is formed over a substrate 205. The substrate may include various circuit elements, such as transistors. A poly-Si plug 270 is formed in the ILD layer, contacting to, for example, a diffusion region of the transistor. The plug is formed by a conventional process which includes: a) forming the contact via in the ILD; b) depositing poly-Si on the substrate to fill the contact opening; and c) planarizing the substrate by chemical mechanical polishing (CMP) to remove excess poly-Si from the surface of the ILD.
The chemicals of the CMP cause a chemical oxide layer 272 to form over as well as in the grain boundaries of the poly-Si plug. The CMP step needs to be sufficiently long to ensure complete removal of the oxide over and in the poly-Si in order to have good contact properties. As shown in FIG. 3, the overpolishing process to remove the oxide from the poly-Si material causes a step 276 to form between the plug and surface of the ILD. This is due to the fact that the etch rate of the ILD material (e.g., silicon oxide) is faster than the etch rate of poly-Si.
After the plug is formed, a metal silicide layer is 380 selectively formed over the plug. The plug further increases the height the step over the plug. Thereafter, the various layers of the capacitors are deposited over the substrate, as shown in FIG. 4.
Such layers, for example, include a barrier 488, a first electrode 461, a dielectric 465, and a second electrode 462. The surface topography of the step is carried through to the various capacitor layers.
However, it has been found that the surface topography resulting from the plug formation can adversely impact the performance of the capacitor. For example, the step can degrade the barrier properties of the barrier layer or change the conductive or dielectric properties of the other layers.
From the foregoing discussion, it is desirable to provide an improved plug which does not adversely affect the properties of the subsequently formed layers.
The invention relates generally to integrated circuits. More particularly, the invention relates to forming capacitor over plug structures. In one embodiment, the capacitor over plug structure comprises a capacitor having a dielectric layer between first and second electrodes. A plug comprising conductive plug material is coupled to the first electrode of the capacitor. In one embodiment, the plug comprises upper and lower portions. The upper portion comprises a surface area substantially equal to that of the first electrode.
In one embodiment, the capacitor comprises a ferroelectric capacitor having a ferroelectric layer between the electrodes. The ferroelectric layer, for example, comprises PZT. A barrier layer can be located between the first capacitor electrode and plug material. The barrier layer prevents oxidation of the plug material. By providing a plug with upper and lower portions in which the upper portion is substantially equal to the surface area of the first electrode advantageously avoids the formation of the step between the plug and ILD layer in conventional capacitor over plug structures. As such, the adverse impact of the step to the properties of the capacitor is reduced or eliminated.